For an early implementation of a long-distance optical fiber transmission system operating at such ultra high speeds as 10 Gb to 40 Gb/s, as it is difficult at the present level of technology to obtain devices having sufficient high-speed characteristics for use in optical transmitter and receiver circuits, there is a need to decrease the operating speed of the entire circuit by reducing the circuitry of high-speed operating blocks to the minimum necessary. Blocks that require the fastest operating speed are the optical transmitter and receiver circuits that directly handle signals at the transmission rate and, in particular, devices operating in synchronism with clock signals tend to be affected by insufficient high-speed characteristics.
FIG. 1 is a diagram showing configuration examples of high-speed optical communication systems according to the prior art.
Part (a) of FIG. 1 concerns an example of a 10 Gb/s optical transmission system, and shows a configuration example of a high-speed optical communication system that uses the so-called fullfrequency clock extraction method that performs data signal discrimination by extracting, from the data signal transmitted at 10 Gb/s, a clock signal of the same frequency as the transmission rate of the transmitted signal.
At an optical transmitter 10, a signal of 10G bit rate (BR) with x signals multiplexed thereon by an x:1 multiplexer (MUX) 11 is waveshaped by a D-flip/flop (D-F/F) 15, and then input to an optical modulator 13 via a driver 14. An optical signal from a laser diode 12 is modulated in the optical modulator 13 by the signal input from the driver, and output as a 10 Gb/s optically modulated signal onto an optical transmission line 20 constructed using an optical fiber.
On the other hand, at an optical receiver 30, the optical signal received from the optical transmission line 20 is converted by a photodiode 31 into an electrical signal which, after being amplified by an amplifier 32, is input to a timing extraction circuit 33 as well as to a discrimination circuit 34. The timing extraction circuit 33 extracts from the input signal a clock signal of 10 GHz which is the same frequency as the transmitted signal. Using the thus extracted clock signal, the discrimination circuit 34 samples the received data signal and discriminates the logic level of the received data signal. After that, the signal is demultiplexed by a 1:x demultiplexing circuit (DEMUX) 35 into the x original signals.
Part (b) of FIG. 1 concerns an example of a higher-speed system, i.e., a 40 Gb/s optical transmission system, and shows a configuration example of a high-speed optical communication system that uses the so-called half-frequency clock extraction method that performs data signal discrimination by extracting, from the data signal transmitted at 40 Gb/s, a clock signal of a frequency equal to one half the transmission rate of the transmitted signal. The following deals only with differences from part (a) of FIG. 1 described above.
First, at the transmitter 10, the D-flip/flop (D-F/F) 15 for waveshaping is omitted. The main reason for this is that, at the present level of technology, it is difficult to fabricate a clocking device that would properly operate at 40 Gb/s (bit width of 25 ps). In the illustrated example, therefore, using the half-frequency clock (BR/2=20 GHz), the signal with x signals multiplexed thereon is selectively output from the multiplexer (MUX) 11 for every half clock cycle, thereby extracting the 40 Gb/s data signal. The data signal directly drives the driver 14, and the 40 Gb/s data signal is output from the optical modulator 13 onto the optical transmission line 20.
Next, at the optical receiver 30, a half-period clock signal (BR/2=20 GHz), one half the bit rate of the received data, is extracted from the received 40 Gb/s data signal by a timing extractor 36 and is output. Then, using normal and inverted clock edge signals for every half cycle period and two discriminators 37 and 38, two data bits (one bit per half cycle period=40 Gb/s) are discriminated for every full clock period. The two discriminated data signals are demultiplexed by a 2:x demultiplexing circuit (DEMUX) 39 at the subsequent stage into the original x signals.
FIG. 2 shows an example of the circuit configuration of the timing extractor 33 and discriminator 34 that uses the full-frequency clock extraction method shown in part (a) of FIG. 1. FIG. 4 is a timing chart showing an example of operation at each point indicated by a parenthesized number in FIG. 2. FIG. 3 shows an example of the circuit configuration of the timing extractor 36 and discriminators 37 and 38 that uses the half-frequency clock extraction method shown in part (b) of FIG. 1. FIG. 5 is a timing chart showing an example of operation at each point indicated by a parenthesized number in FIG. 3. The basic operation of these circuits will be described briefly below.
The received data signal (1) is input to a two-stage cascade of D-flip/flops 41 and 42, which corresponds to the discrimination circuit 34 in part (a) of FIG. 1, and a signal (3) synchronized to the clock and a signal (4) delayed by one bit from the signal (3) are generated using a clock rising edge signal from a PLL (Phase Locked Loop) circuit in the lower part of the figure. The received data signal (1) is also input to another twostage cascade of D-flip/flops 43 and 44. Here, however, the first-stage D-flip/flop 43 is latched by a clock falling edge signal, and the second-stage D-flip/flop 44 is latched by a clock rising edge signal. As a result, a synchronized signal (5) delayed by a half cycle period from the synchronized signal (3) and a synchronized signal (6) delayed by a further half cycle period (thus in phase with the synchronized signal (4)) are generated. Next, the synchronized signals (4) and (6) are exclusive-ORed together to produce an EXOR output signal (8), and the synchronized signals (3) and (6) are exclusive-ORed together to produce an EXOR output signal (7); these output signals are compared in a comparator circuit 47, and the result of the comparison is fed via a loop filter 48 to control a voltage-controlled oscillator (VCO) 49.
Here, by noting the phase relationship between the rising/falling edge of the received data signal (1) and the falling edge of the clock signal (2), use is made of the fact that the EXOR output signals (7) and (8) vary depending on which edge comes first. As shown in part (a) of FIG. 4, when the falling edge of the clock output signal (2) from the VCO 49 is delayed with respect to the changing edge of the received data signal (1) (delayed in phase), the synchronized signals (3) and (6) are identical to each other, and the EXOR output signal (7) is therefore at a low level. Conversely, as shown in part (b) of FIG. 4, when the falling edge of the clock output signal (2) from the VCO 49 is advanced with respect to the changing edge of the received data signal (1) (advanced in phase), the synchronized signals (4) and (6) are identical to each other, and the EXOR output signal (8) is therefore at a low level. On the other hand, when the input signal pattern is random, and its mark-space ratio is 1/2, in the case of the delayed phase the average voltage of the EXOR output signal (8) is at a value intermediate between the high and low levels. In the case of the advanced phase, on the other hand, the average voltage of the EXOR output signal (7) is at a value intermediate between the high and low levels. Accordingly, the phase relationship between the data signal and the clock signal can be detected based on the difference between the average voltages of the EXOR output signals (7) and (8). In the illustrated example, the result of the comparison from the comparator circuit 47, constructed using a binary phase comparator circuit, is fed via the loop filter (low-pass filter) 48 to control the VCO 49 in such a manner as to reduce the phase difference to zero. More specifically, in the illustrated example, the phase is controlled so that the falling edge of the clock output signal (2) always coincides with the changing edge of the received data signal (1), and signal discrimination is performed using the two edge signals appearing before and after the falling edge.
Next, an example of the circuit operation of the half-frequency clock extraction method shown in FIGS. 3 and 5 will be described. Here, the oscillation center frequency of the VCO 50 is equal to one half the bit rate of the received data signal (1). The received data signal (1) is input to two D-flip/flops 51 and 52, which correspond to the discrimination circuits 37 and 38 in part (b) of FIG. 1, and signals (3) and (4) respectively synchronized to the falling and rising edge signals from the PLL circuit in the lower part of the figure are generated. The received data signal (1) is also input to a D-flip/flop 53; here, the clock signal output from the VCO 50 is supplied via a T/2 delay circuit 54 (T/2=¼ clock cycle period, T=half clock cycle period), and a signal (6) synchronized to the rising edge of the clock signal is generated.
The process thereafter is the same as that described with reference to FIG. 2; that is, the exclusive OR (EXOR) output signal (8) between the synchronized signals (4) and (6) and the EXOR output signal (7) between the synchronized signals (3) and (6) are produced, and the comparator circuit 47 compares these output signals and supplies the result of the comparison via the loop filter 48 to control the voltage-controlled oscillator (in this example, the VCO 50). As shown in part (a) of FIG. 5, when the rising edge of the ¼ cycle delayed clock signal (5) from the VCO 50 is delayed with respect to the changing edge of the received data signal (1), the synchronized signals (3) and (6) coincide with each other for a ¾ clock cycle period, during which the EXOR output signal (7) is held at the low level. Conversely, as shown in part (b) of FIG. 5, when the rising edge of the clock signal (5) from the VCO 50 is advanced with respect to the changing edge of the received data signal (1), the synchronized signals (4) and (6) coincide with each other for a ¾ clock cycle period, during which the EXOR output signal (8) is held at the low level. The result of the comparison from the comparator circuit 47 is fed to control the VCO 50 at the subsequent stage in such a manner as to reduce the phase difference to zero. More specifically, in the illustrated example, the phase controlled so that the rising edge of the clock signal always coincides with the changing edge of the received data signal (1), and signal discrimination is performed using the two edge signals appearing before and after the rising edge. In this way, the half-frequency clock extraction method offers an enormous advantage in that the half-frequency clock can be used while using the substantially the same hardware configuration as that for the full-frequency clock method.
However, the half-frequency clock extraction method has had the problem that when comparing the phase between the clock signal and the data signal, if a specific data signal pattern “1100” is repeated in succession, the phase comparison signal cannot be obtained, which has not beer the case with the traditional full-frequency clock extraction method.
FIGS. 6 and 7 show timing chart examples of two phase relationships A and B for the signal pattern “1100” in question. FIG. 6 shows the case where the clock signal is delayed in phase (a) and the case where it is advanced in phase (b); in the illustrated example, as the rising edge of the clock signal (5) is within the phase control range relative to the change point (“0” to “1” or “1” to “0”) of the received data signal (1), a difference 35 occurs between the level average values of the synchronized signals (7) and (8) (phase relationship A). Therefore, as in the case of FIG. 5, by comparing the levels of the synchronized signals (7) and (8), phase control is performed so that the clock rising edge coincides with the changing edge of the received data signal (1). FIG. 7 also shows the case where the clock signal is delayed in phase (a) and the case where it is advanced in phase (b), but in this example, as the rising edge of the clock signal (5) occurs at the same-level transitioning point (“0” to “0” or “1” to “1”) of the received data signal (1), the synchronized signals (7) and (8) are the same in waveform, and therefore, their level average values are also the same (phase relationship B). As a result, during that period, phase detection cannot be performed, giving rise to the possibility of the PLL running out of synchronization.
In this way, for phase comparison, a low-to-high or a high-to-low level transition of the data signal is needed, but in the case of the half-frequency clock extraction method, all the data signal changes are not used for phase comparison, but only one in every two changes is used, as shown in FIGS. 6 and 7. As a result, while the phase can be detected in the case of the phase relationship A of FIG. 6, the phase cannot be detected in the case of the phase relationship B of FIG. 7. One possible way to address this problem would be to scramble the data signal, but in the example of a 10 Gb/s optical transmission system, the “1100” pattern is actually used over a length of 1528 bits (in the case of a system conforming to Bellcore Generic Requirements GR-1377-CORE, “SONET OC-192 Transport System Generic Criteria”), and in the case of a higher-speed system also, there is the possibility of the “1100” pattern being used over a length of several thousand bits in succession. If the half-frequency clock extraction method is used for such systems, there can arise the problem that the phase deviation of the PLL increases or the PLL runs out of synchronization, as described above.
As another problem, in the case of the system configuration shown in part (b) of FIG. 1 for performing ultra high-speed optical communications at 40 Gb/s, waveshaping by a D-F/F clocked at the data transmission rate is not performed at the final stage of the optical transmitter 10. This can lead to a problem such as shown in FIGS. 8 and 9.
FIG. 8 is a diagram showing a circuit configuration example of an output stage of a 2:1 multiplexing circuit. FIG. 9 shows a waveform example of each signal shown in FIG. 8 and the clock versus data discrimination timing relationship according to the half-frequency clock extraction method at the optical receiver side.
In FIG. 8, 20 Gb/s serial data (DATAL) is input to a D-flip/flop 61, while 20 Gb/s serial data (DATA2) is input to a D-flip/flop 62. In the illustrated example, the 20 GHz clock signal shown in part (a) of FIG. 9, whose duty cycle is deviated, is applied as is to the clock terminal of the D-flip/flop 61, and its inverted clock signal is applied to the clock terminal of the D-flip/flop 62. The clock signal is also applied to control a selector 64 via a delay circuit (T/4=⅛ clock cycle period) 63 provided to compensate for the operation delay times of the D-flip/flops 61 and 62, and the selector 64 selects one or the other of the outputs of the two D-flip/flops 61 and 62 for output by switching between them for every half clock cycle. As a result, 40 Gb/s data is output from the selector 64, but as shown in part (b) of FIG. 9, a data signal whose duty cycle is deviated is output every other bit because of the duty deviation of the clock signal.
When discriminating the received data at the optical receiver 30 by using the half-frequency clock extraction method, the problem has been that, as shown in part (c) of FIG. 9, there is no sampling margin at one of the data discrimination (sampling) points located symmetrically about the PLL phase lock clock signal at the center. As a result, even if the data discrimination phase for either one is adjusted, since there are two phase lock points (change points from “narrow to wide” or “wide” to “narrow” of the duty cycle) in the half-frequency clock extraction method, it has not been possible to solve the problem of the data discrimination phase eventually deviating from the set point.